Background Digital Calibration Techniques for Pipelined ADC’sy

A skip and fill algorithm is developed to digitally self-calibrate pipelined analog-to-digital converters (ADC’s) in real time. The proposed digital calibration technique is applicable to capacitor-ratioed multiplying digital-to-analog converters (MDAC’s) commonly used in multi-step or pipelined ADC’s. This background calibration process can replace, in effect, a trimming procedure usually done in the factory with a hidden electronic calibration. Unlike other self-calibration techniques working in the foreground, the proposed technique is based on the concept of skipping conversion cycles randomly but filling in data later by nonlinear interpolation. This opens up the feasibility of digitally implementing calibration hardware and simplifying the task of self-calibrating multi-step or pipelined ADC’s. The proposed method improves the performance of the inherently fast ADC’s by maintaining simple system architectures. To measure errors resulting from capacitor mismatch, op amp dc gain, offset, and switch feedthrough in real time, the calibration test signal is injected in place of the input signal using a split-reference injection technique. Ultimately, the missing signal within 2/3 of the Nyquist bandwidth is recovered with 16-bit accuracy using a 44-th order polynomial interpolation, behaving essentially as an FIR filter. This work was supported by the National Science Foundation under Grant MIP-9312671.